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hyb18h1g321a2f?08 hyb18h1g321a2f?10 hyb18h1g321a2f?14 gddr3 graphics ram 1-gbit gddr3 graphics ram eu rohs compliant advance internet data sheet rev. 0.61 october 2008
advance internet data sheet hyb18h1g321a2f 1-gbit gddr3 graphics ram qag_techdoc_a4, 4.22, 2008-07-22 2 10102008-h7r1-i6ah we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com hyb18h1g321a2f?08, hyb18h1g321a2f?10, hyb18h1g321a2f?14 revision history: 2008-10, rev. 0.61 page subjects (major chang es since last revision) all adapted internet version hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 3 10102008-h7r1-i6ah 1overview this chapter lists all main features of the product family hyb18h1g321a2f and the ordering information. 1.1 features ? 1.8 v and 1.5 v v ddq io voltage hyb18h1g321a2f?08 ? 1.8 v and 1.5 v v dd core voltage hyb18h1g321a2f?08 ? monolithic 1gbit gddr3 with an internally programmable organization of either two separate 512mbit memories (2048 k x 32 i/o x 8 banks) with separate chip select, or one 1gb memory (4096 k x 32 i/o x 8 banks) ? two cs: 4096 rows and 512 columns (128 burst start locations) per bank ? one cs: 8192 rows and 512 columns (128 burst start locations) per bank ? differential clock inputs (clk and clk ) ? cas latencies of 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 ? write latencies of 3, 4, 5, 6, 7 ? burst sequence with length of 4, 8 ? 4n pre fetch ? short ras to cas timing for writes ? t ras lockout support ? t wr programmable for writes with auto-precharge ? data mask for write commands ? single ended read strobe (rdqs) per byte. rdqs edge- aligned with read data ? single ended write strobe (wdqs) per byte. wdqs center-aligned with write data ? dll aligns rdqs and dq transitions with clock ? programmable io interface including on chip termination (odt) ? autoprecharge option with co ncurrent auto precharge support ? 8k refresh (32ms) ? autorefresh and self refresh ? pg-tfbga-136 package ? calibrated output drive. active termination support ? rohs compliant product 1) 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 4 10102008-h7r1-i6ah table 1 ordering information part number 1) 1) hyb: designator for memory components 18h: v dd / v ddq = 1.8v 1g: 1 gbit 32: x32 organization a2: product revision f: lead and halogen-free organization clock (mhz) package hyb18h1g321a2f?08 32 1200 @ cl15, 1.8 v pg-tfbga-136 900 @ cl11, 1.5 v hyb18h1g321a2f?10 x32 1000 @ cl12, 1.8 v 800 @ cl10, 1.5 v hyb18h1g321a2f?14 x32 700 @ cl10, 1.8 v 700 @ cl10, 1.5 v hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 5 10102008-h7r1-i6ah 1.2 description the qimonda 1-gbit gddr3 graphics ram is a high speed memory device, designed for high bandwidth intensive applications like pc graphics systems. the chip is programmable into two different configurations. in the default mode the architecture is organized as two 512 mbit me mories of 8 banks, each (two cs mode). in an alternate configuration, it behaves as a conventional, 8-bank 1 gbit dram (one cs mode). hyb18h1g321a2f uses a double data rate interface and a 4 n -pre fetch architecture. the gddr3 interface transfers two 32 bit wide data words per clock cycle to/fro m the i/o pins. corresponding to the 4 n -pre fetch a single write or read access consists of a 128 bit wide, one-clock-cycle data transfer at the internal me mory core and four corresponding 32 bit wide, one-half-clock - cycle data transfers at the i/o pins. single-ended unidirectional read and write data strobes are transmitted simultaneously with read and write data respectively in order to capture data properly at the receivers of both the graphics sdram and the controller . data strobes are organized per byte of the 32 bit wide interface. for read commands th e rdqs are edge-aligned with data, and the wdqs are center- aligned with data for write commands. the hyb18h1g321a2f operates from a differential clock (clk and clk ). commands (addresses and control signals) are registered at every positive edge of clk. input data is registered on both edges of wdqs, and output data is referenced to both edges of rdqs. in this document references to ?the positive edge of clk? impl y the crossing of the positive edge of clk and the negative edge of clk . similarly, the ?negative edge of clk? refers to the crossing of the negative e dge of clk and the positive edge of clk . references to rdqs are to be interpreted as any or all rdqs< 3:0>. wdqs, dm and dq should be interpreted in a similar fashion. read and write accesses to the hyb18h1g321a2f are burst ori ented. the burst length is fixed to 4 and 8 and the two least significant bits of the burst address are ?don?t care? and inte rnally set to low. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and the row to be accessed. the address bits registered coincident with the read or write command are used to sele ct the bank and the column location for the burst access. in two cs mode, each of the 2 x 8 banks consists of 4096 row locations and 512 column locations. in one cs mode, the number of row locations doubles to 8192 rows while the number of column location remains unchanged at 512 columns. an auto precharge function can be combined with read and write to provide a self-timed row prec harge that is initiated at th e end of the burst access. the pipe lined, multibank architecture of the hyb18h1g321a2f allows for concurrent operation, t hereby providing high effective bandwidth by hiding row precharge and activation time. the ?on die termination? interface (odt) is optimized for high fr equency digital data transfers and is internally controlled. t he termination resistor value can be set using an external zq re sistor or disabled through the extended mode register. the output driver impedance can be set using the extended mode register. it can either be set to zq / 6 (auto calibration) or to 35, 40 or 45 ohms. auto refresh and power down with self refresh operations are supported. an industrial standard pg-tfbga-136 package is used which enables ultra high speed data transfer rates and a simple upgrade path from former ddr graphics sdram products. hyb18h1g321a2f 1-gbit gddr3 graphics ram advance internet data sheet rev. 0.61, 2008-10 6 10102008-h7r1-i6ah 2 configuration figure 1 ballout 1-gbit gddr3 graphics ram in 1-cs mode in non merged mode(top view; mf = low) 0 3 3 * & |